1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, and in particular, it is related to a layout and connecting structure between inner lead terminals of the package and bonding pads on a chip for an ultra high speed semiconductor integrated circuit device of a speed greater than 100 Gigabit/sec.
2. Description of the Prior Art
As the scale of integration of the semiconductor device has increased, improving of the efficiency and the processing speed of the device has become important. In the field of the ultra high speed semiconductor IC devices, gallium arsenide (GaAs) is used widely for practical use, since its carrier mobility is larger than that of silicon. It has been reported that GaAs semiconductor devices have operated at more than 10 Gigabit/sec (G bit/s) without difficulty, but it is still difficult to operate the GaAs IC devices at 100 G bit/s.
On the other hand, as the scale of integration of semiconductor devices has increased, interconnection wiring between elements has become complicated, and it has become a serious problem to be solved in an ultra high speed IC device.
In order to more clearly understand the advantage of the present invention, the prior art wiring of a semiconductor device will be described briefly. FIG. 1 illustrates schematically a cross-sectional view of a prior art structure of an exemplary semiconductor IC device. FIG. 2 illustrates schematically a cross-sectional view of a multilead IC device which has a wiring board. FIG. 3A is a schematic cross-sectional view of a prior art wiring board corresponding to FIG. 2. FIG. 3B illustrates schematically a bottom plan view of the conventional structure of a wiring board corresponding to FIG. 3A.
In the figures, reference numerals 1 and 11 are the package, 2 and 12 are the semiconductor chips mounted in the package, 3 and 13 are outer leads, 4 and 14 are inner lead terminals connected to the outer leads, 5 and 15 are bonding pads, and 6 and 19 are inner leads connected between the bonding pads 5 or 15 and the inner lead terminal 4 or 14 of the package. 7 and 17 are cover plates which cover the package 1 or 11. 16 is a wiring board which includes a dielectric plate 18, a positioning mark 18a, signal lines 19 and 19a, signal line terminal 19aa, and a projection lead 19ab for bonding to the chip 2 or 12 (see FIGS. 3A, 3B). 50 is a cavity, 60 is a low melting point metal sheet to bond the chip, and 70 is a hermetic seal.
In a conventional GaAs IC device, as shown in the FIGS. 1 through 3, a GaAs substrate chip 2 or 12 is bonded by the low melting point metal sheet 60 in the cavity 50 of the ceramic package 1 or 11. Each of the bonding pads 5 or 15 on the chip 2 or 12, have the inner leads 6 or 19 respectively interconnected to the outer leads 3 or 13 through the inner lead terminals 4 or 14. A wiring board 16 is provided with a printed wiring circuit to connect the wiring line between the bonding pad 15 and the outer leads 13. The wiring board 16 is arranged above the chip 12. The chip size is approximately 4 mm square for example. The package 1 or 11 is sealed hermetically to the cover plate 7 or 17 respectively by a seal 70.
As the integration scale of the semiconductor device has increased, the wiring between the chip 2 and outer lead 3 has become more complicated. Applying the wiring board of the prior art as shown in FIG. 2, the wiring of the device is simplified. In most of the prior art devices, a multi-lead package having a wiring board 16 is used such as shown in FIG. 2.
A study of currently available IC packages has developed the performance characteristics for GaAs ICs operating at ultra high speed. When the operation speed is increased up to an ultra high speed operation of approximately 100 G bit/s, the conventionally structured device has disadvantages, such as large reflection and attenuation of the signal on its transmission lines in the package. Accordingly, it is necessary to reduce transmission loss, and the reflection and attenuation of the signal on the inner leads 6 and 19 which are connected between the outer leads 3 or 13 and bonding pads 5 or 15 respectively.